Principles of Computer Organization (Second Edition) Tang shuofei Page 73 main memory has an address allocation for a storage unit in main memory. It gives an example: for 24 bit address line Is this example wrong? Yes, explain it to me

No mistake! In 4-6a, the word length of the computer is 4 bytes; in B, the word length of the computer is 2 bytes (look at the picture carefully)!
If it's self-study, it's almost certain that we'll have trouble here. The word length here is 8 bits for a byte and 16 bits for a word. It doesn't mean the same thing. It varies from computer to computer

After class exercises of the second edition of computer composition principle!
In Chapter 3, system bus 3.7, draw a diagram to explain the interlocking relationship between request and answer in asynchronous communication?

Non interlocking, semi interlocking and full interlocking
The picture is on page 62 of the textbook!
(1) Asynchronous communication is simple, both sides clock can allow a certain error. Synchronous communication is more complex, both sides clock error is small
(2) Asynchronous communication only applies to point, synchronous communication can be used for point
(3) Communication efficiency: low asynchronous communication, high synchronous communication

Principles of computer composition
There is a microcomputer principle problem, very urgent, please know the answer!
The current CS value is 1000h, the IP value is 2300h, and the current instruction is a three byte instruction. What is the next instruction's instruction fetch (command) address (physical address)?
Supplement: is the next instruction's fetch address related to the current instruction's three byte instruction? If the title is changed to: the current CS value is 1000h, the IP value is 2300h, the current instruction is one byte instruction, what is the next instruction's fetch address (physical address)? What is the answer?

The current CS value is 1000h, the IP value is 2300h, the current instruction is three byte instruction, the next instruction's fetch address (physical address) is 12303h, the next instruction's fetch address is related to the current instruction's three byte instruction, if the title is changed to: the current CS value is 1000h, the IP value is 2300h, the current instruction is one

Suppose that the word length of an instruction system is 12 bits and each address field is 3 bits, a scheme is designed to make it have 4 3-address instructions, 8 double address instructions and 180 single address instructions
This is about the principle of computer composition

The plan is as follows:
1. Three address instruction: the operation code occupies three digits, and the address code occupies eight digits. The operation code is 000000100011
2. Double address instruction: the operation code occupies 6 bits and the address code occupies 8 bits. The operation code is 100000100001100010100011100100101100110100111.8
3. Single address instruction: 9 bits for operation code and 3 bits for address code
101000000 --- 101111111,64
110000000 --- 110111111,64
111000000 --- 111110011,52

Principle of Computer Organization
A computer system uses 16 bit single sub long instruction, address code is 4 bits
1. If 10 kinds of three address orders are defined, how many more two address orders can there be, assuming that there are no single address order and zero address order
2. If it needs to add 60 two address commands, how many single address commands can there be, assuming that there is no zero address command

1. 16 bit single word address code, 4-bit three address instructions occupy 12 bits, and the remaining 4 bits are operation codes, so there are 16 clock operation modes. After 10 kinds of operation codes are defined, there are 6 kinds of expandable operation codes, that is, there are 96 kinds of two address code instructions, and the high 4-bit operation codes of 10 three address instructions are 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001. After expansion, the high order can not be repeated, so we should start from 1010 10100000-11111111
2. If 60 two address instructions are needed, the remaining two address instructions are 36, namely 11011100-11111111
After expansion, it is 11011100xxx-11111111xxx, that is, the two address instructions are 36 * 2 * 2 * 2 * 2 = 576 two address instructions
I don't have the right answer. Let's discuss together. If you don't understand what's wrong, you say we should continue to study

(101 0111100 1000100 1100101 1001) 2 convert it to decimal
(101 0111,100 1000,100 1001,100 1100,101 1001) 2

Your words are ambiguous: one refers to: (1010111) decimal = 87; (1001000) decimal = 72; (1001001) decimal = 73; (1001100) decimal = 76; (1011001) decimal = 89; two refers to: (101011110000100111001011001) decimal = 2 [0] + 2 [...]

How to convert 2 to 10 base 1101 / 1000 / 0110 (b)
How to convert 2 to 10 base 110
How to convert 2 to 10 base 1101 / 1000 / 0110 (b)?
How to turn 2 to 10 base 110

In principle, the weight of binary system is the same as that of decimal system. From right to left, the weight of binary system is 1 (to the 0 th power of 2), 2 (to the 1 th power of 2), 2 * 2, 2 * 2 * 2, '"' ', so the answer is 1101:1 * 2 * 2 * 2 + 1 * 2 * 2 + 0 * 2 + 1 * 1 = 131000:1 * 2 * 2 * 2 * 2 + 0 * 2 + 0 * 2 + 0 * 1 = 80110:0 * 2 * 2 * 2 + 1 * 2 *

What is the result of converting binary [1001] to decimal?

Well 1001 square It seems that 1010001… Convert to decimal 1＊64＋1＊16＋1＊1＝81…
I don't know, right

Principles of Computer Organization (Second Edition) Tang shuofei Page 73 main memory has an address allocation for a storage unit in main memory. It gives an example: for 24 bit address line Is this example wrong? Yes, explain it to me