Using JK flip-flop and additional gate circuit to design a 7-ARY addition counter, the detailed steps to solve the problem, thank you

Using JK flip-flop and additional gate circuit to design a 7-ARY addition counter, the detailed steps to solve the problem, thank you

The specific process is like that

Can a counter be made up of D flip flops?

Yes. The function of counter can be realized by counting the high level (count 1) or low level (count 0) of the final output Q or Q not of the cascade structure composed of n d flip flops. For example, if the frequency of clock source is 100Hz, the final output will count with the frequency of 100g2 to the nth power

What is the difference between the counter composed of D trigger and JK Trigger?

JK flip-flop is to connect both J and K ends to 1 to realize reverse phase. D flip-flop is to connect ~ Q end to d end of this flip-flop to realize reverse phase directly. The principle is the same, but the connection method is different

Design an 8-bit subtraction counter circuit (7,6 0 loop). Realized by D flip-flop

D-flip-flop can be used as a binary subtraction counter. The second level D-flip-flop CP can be connected to the first level q-end, but the D-flip-flop has to be connected into a t 'flip-flop